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LE25FW403A Datasheet(PDF) 6 Page - Sanyo Semicon Device |
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LE25FW403A Datasheet(HTML) 6 Page - Sanyo Semicon Device |
6 / 18 page LE25FW403A No.A1229-6/18 5 Bus Read 2. Status Registers Device status can be detected using status registers. Table 3 gives the contents of status registers. Table 3 Status Registers Bit Name Logic Function Power-on Time Information 0 Ready Bit0 RDY 1 Erase/Program/Write 0 0 Write disabled Bit1 WEN 1 Write enabled 0 Bit2 0 Reserved bits 0 Bit3 0 Reserved bits 0 Bit4 0 Reserved bits 0 Bit5 0 Reserved bits 0 Bit6 0 Reserved bits 0 Bit7 0 Reserved bits 0 2-1. Status Register Read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. • Page erase • Sector erase • Chip erase • Page program • Page write Figure 6 shows the timing waveforms of the status register read. Consisting only of the first bus cycle, the status register read command outputs the contents of the status register from bit 7 synchronized to the falling edge of the clock (SCK) when (05h) is input. If the clock (SCK) is continued after data up to RDY (bit 0) are output, the data is output by returning to the bit 7. Data is output from the falling clock of the first bus cycle bit 0. N+2 N+1 N CS High Impedance DATA DATA DATA SCK SO SI 0Bh Add. Add. Add. X 15 MSB MSB MSB 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 48 55 Mode3 Mode0 8CLK |
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