PRELIMINARY
CY2XF23
Document Number: 001-53145 Rev. *A
Page 6 of 11
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
SCLK
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
STOP
START
ACK
D7
D6
D1
D0
++
+
+
+
+
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN
[2]
Input Voltage, DC
Relative to VSS
–0.5
VDD+0.5
V
TS
Temperature, Storage
Non Operating
–55
135
°C
TJ
Temperature, Junction
–40
135
°C
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
2000
V
Θ
JA
[3]
Thermal Resistance, Junction to Ambient
0 m/s airflow
64
°C/W
Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
VDD
3.3V Supply Voltage Range
3.135
3.3
3.465
V
2.5V Supply Voltage Range
2.375
2.5
2.625
V
TPU
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
0.05
–
500
ms
TA
Ambient Temperature (Commercial)
0
–
70
°C
Ambient Temperature (Industrial)
–40
–
85
°C
Notes
2. The voltage on any input or I/O pin cannot exceed the power pin during power up.
3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors.
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
IDD
[4]
Operating Supply Current
VDD = 3.465V, CLK = 150 MHz, output
terminated
–
–
120
mA
VDD = 2.625V, CLK = 150 MHz, output
terminated
––
115
mA
VOD
LVDS Differential Output Voltage
VDD = 3.3V or 2.5V, defined in Figure 8
as terminated in Figure 13
250
–
450
mV
ΔV
OD
Change in VOD between Comple-
mentary Output States
VDD = 3.3V or 2.5V, defined in Figure 8
as terminated in Figure 13
––
50
mV
VOS
LVDS Offset Output Voltage
VDD = 3.3V or 2.5V, defined in Figure 9
as terminated in Figure 13
1.125
–
1.375
V
ΔV
OS
Change in VOS between Comple-
mentary Output States
VDD = 3.3V or 2.5V, RTERM = 100Ω
between CLK and CLK#
––
50
mV
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