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CY2XP24ZXC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY2XP24ZXC
Description  Crystal to LVPECL Clock Generator
Download  8 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2XP24ZXC Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY2XP24
Document #: 001-15705 Rev. *D
Page 5 of 8
Figure 7. Output Duty Cycle
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Because all current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
Termination for LVPECL Output
The CY2XP24 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
to VDD–2.0V. This termination voltage can also be used for VDD
= 2.5V operation, or it can be terminated to VDD-1.5V. Note that
it is also possible to terminate with 50 ohms to ground (VSS), but
the high and low signal levels differ from the data sheet values.
Termination resistors are best located close to the destination
device. To avoid reflections, trace characteristic impedance (Z0)
should match the termination impedance. Figure 9 shows a
standard termination scheme.
Figure 9. LVPECL Output Termination
Crystal Input Interface
The CY2XP24 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
therefore layout dependent.
Figure 10. Crystal Input Interface
CLK
T
PW
T
PERIOD
T
DC =
T
PW
T
PERIOD
CLK#
3.3V
10µF
0.1μF
VDD
V DD
0.01 µF
(Pin 1)
(Pin 8)
CLK
84
Ω
84
Ω
Z0 = 50
Ω
Z0 = 50
Ω
3.3V
125
Ω
125
Ω
IN
CLK#
Device
XIN
XOUT
X1
18 pF Parallel
Crystal
C1
30 pF
C2
27 pF
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