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ISL95811 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL95811 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 14 page 11 FN6759.1 October 6, 2008 Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 17). On power-up of the ISL95811, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95811 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 17). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 17). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 18). The ISL95811 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95811 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 4). TABLE 4. IDENTIFICATION BYTE FORMAT 0 1 0 1000 R/W (MSB) (LSB) FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER SDA SCL START DATA DATA STOP STABLE CHANGE DATA STABLE SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER 8 1 9 START ACK SCL FROM MASTER HIGH IMPEDANCE HIGH IMPEDANCE ISL95811 |
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