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KAD5512HP-21Q48 Datasheet(PDF) 7 Page - Intersil Corporation |
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KAD5512HP-21Q48 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 32 page  7 FN6808.2 March 4, 2009 Timing Diagrams FIGURE 1A. DDR FIGURE 1B. SDR FIGURE 1. LVDS TIMING DIAGRAMS FIGURE 2A. DDR FIGURE 2B. SDR FIGURE 2. CMOS TIMING DIAGRAM LATENCY = L CYCLES tDC tPD tA SAMPLE N tCPD INP INN CLKN CLKP CLKOUTN CLKOUTP ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS D[10/8/6/4/2/0]P D[10/8/6/4/2/0]N N LATENCY = L CYCLES tDC tPD tA SAMPLE N tCPD INP INN CLKN CLKP CLKOUTN CLKOUTP DATA DATA N-L + 1 D[11/0]P D[11/0]N N DATA N-L SAMPLE N tDC tPD tA INP INN CLKN CLKOUT CLKP D[10/8/6/4/2/0] LATENCY = L CYCLES ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS N tCPD SAMPLE N INP INN CLKN CLKOUT CLKP tCPD tA D[11/0] tDC tPD DATA N-L DATA DATA N-L + 1 N LATENCY = L CYCLES Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS ADC OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 60 fs Output Clock to Data Propagation Delay, LVDS Mode (Note 10) DDR Rising Edge tDC -260 -50 120 ps DDR Falling Edge tDC -160 10 230 ps SDR Falling Edge tDC -260 -40 230 ps Output Clock to Data Propagation Delay, CMOS Mode (Note 10) DDR Rising Edge tDC -220 -10 200 ps DDR Falling Edge tDC -310 -90 110 ps SDR Falling Edge tDC -310 -50 200 ps KAD5512HP |
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