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UC5605DP Datasheet(PDF) 1 Page - Texas Instruments |
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UC5605DP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 5 page • Reverse Disconnect • Complies with SCSI, SCSI-2 and SPI-2 Standards • 5pF Channel Capacitance during Disconnect • Hot Plugging Capability •−400mA Sourcing Current for Termination • +100mA Sinking Current for Active Negation • 1V Dropout Voltage Regulator • 100 µA Supply Current in Disconnect Mode • Trimmed Termination Current to 5% • Trimmed Impedance to 5% • Low Thermal Resistance Surface Mount Packages The UC5605 provides 9 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recommends active termi- nation at both ends of the cable segment. The only functional differences between the UC5603 and UC5605 is the ab- sence of the negative clamps on the output lines and the disconnect input must be at a logic-low for the terminating resistors to be disconnected. Parametri- cally, the UC5605 has a 5% tolerance on impedance and current compared to a 3% tolerance on the UC5603. Custom power packages are utilized to allow normal operation at full power (2 Watts). The UC5605 provides a disconnect feature which, when driven low, discon- nects all terminating resistors, disables the regulator and greatly reduces standby power consumption. The output channels remain high impedance even without Termpwr applied. A low channel capacitance of 5pF allows interim points of the bus to have little to no effect on the signal integrity. Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance, and then most importantly, to trim the output current to a 5% tolerance, as close to the maximum SCSI specification as possible. This maximizes the noise mar- gin in fast SCSI operation. Other features include thermal shutdown and cur- rent limit. This device is offered in low thermal resistance versions of the industry stand- ard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin TSSOP. UC5605 9-Line Low Capacitance SCSI Active Terminator FEATURES DESCRIPTION BLOCK DIAGRAM Circuit Design Patented 3/97 UDG-94122 |
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