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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Document #: 38-06031 Rev. *E
Page 8 of 15
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) [12, 20]
Switching Waveforms (continued)
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
tPS
tBLA
tRC
tPWE
VALID
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE
CE
R/W
ADDRESS
OE
DOUT
DATAIN
Note
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
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