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CY7C1012DV33
Document Number: 38-05610 Rev. *D
Page 7 of 11
Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
WE
DATA I/O
ADDRESS
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O
NOTE 18
Notes
16. Data I/O is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18. During this period, the I/Os are in output state. Do not apply input signals.
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