CY7C1034DV33
Document Number: 001-08351 Rev. *C
Page 4 of 9
Figure 2. AC Test Loads and Waveform [4]
AC Switching Characteristics
Over the operating range [5]
Parameter
Description
–10
Unit
Min
Max
Read Cycle
tpower [6]
VCC(Typical) to the First Access
100
μs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
10
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE Active LOW to Data Valid [3]
10
ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low Z [7]
1ns
tHZOE
OE HIGH to High Z [7]
5ns
tLZCE
CE Active LOW to Low Z [3, 7]
3ns
tHZCE
CE Deselect HIGH to High Z [3, 7]
5ns
tPU
CE Active LOW to Power Up [3, 8]
0ns
tPD
CE Deselect HIGH to Power Down [3, 8]
10
ns
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
(a)
(b)
R1 317
Ω
R2
351
Ω
Fall Time:> 1V/ns
(c)
OUTPUT
50
Ω
Z0= 50Ω
VTH = 1.5V
30 pF*
*Capacitive Load consists of all
components of the test environment
Rise Time > 1V/ns
*Including jig
and scope
Notes
4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0V). 100 μs (tpower) after reaching the minimum operating VDD,
normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of the AC Test Loads and Waveform [4], unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady
state voltage.
8. These parameters are guaranteed by design and are not tested.
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