CY7C1354DV25
CY7C1356DV25
Document #: 001-48974 Rev. *A
Page 6 of 29
Pin Definitions
Pin Name
IO
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
BWa,BWb,
BWc,BWd,
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
Input-
Synchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance or Load Input used to Advance the On-Chip Address Counter or Load a New Address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be driven
LOW in order to load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select and deselect the device.
CE2
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select and deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select and deselect the device.
OE
Input-
Asynchronous
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control
the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a Write
sequence, during the first clock when emerging from a deselected state and when the device is
deselected.
CEN
Input-
Synchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQS
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[a:d]. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE is default HIGH, to an interleaved burst order.
TDO
JTAG Serial
Output
Synchronous
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
TDI
JTAG Serial
Input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK.
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