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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Document #: 001-12561 Rev. *F
Page 2 of 26
Logic Block Diagram (CY7C1410JV18)
Logic Block Diagram (CY7C1425JV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
21
16
8
NWS[1:0]
VREF
Write
Reg
8
A(20:0)
21
CQ
CQ
DOFF
Q[7:0]
8
8
8
Write
Reg
C
C
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
18
9
BWS[0]
VREF
Write
Reg
9
A(20:0)
21
CQ
CQ
DOFF
Q[8:0]
9
9
9
Write
Reg
C
C
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