4

UCC1570

UCC2570

UCC3570

RAMP: Ramp Pin. Connect a capacitor to GND. Rising

slope is programmed by current in SLOPE. This slope is

compared to FEEDBK for pulse width modulation. The

falling slope is programmed by the current in ISET and

used to limit maximum duty cycle.

FREQ: Oscillator pin. Program the frequency with a ca-

pacitor to GND.

VREF: Precision 5V reference, and bypass point for inter-

nal circuitry. Bypass this pin with a 1

µF minimum capaci-

tor to GND.

GND: Analog ground. Connect to a low impedance

ground plane containing all analog low current returns.

SOFTST: Soft start pin. Program with a capacitor to

GND.

COUNT: Program the time that fault events will be toler-

ated before shutdown occurs with a capacitor and resis-

tor to GND.

CURLIM: Current Limit Sense pin. Terminates OUT gate

drive pulse for inputs over 0.2V. Enables fault counting

function (COUNT). For inputs over 0.6V, the shutdown

latch is activated.

PIN DESCRIPTIONS (cont.)

(Note: Refer to Typical Application for external compo-

nent names.) All the equations given below should be

considered as first order approximations with final values

determined empirically for a specific application.

Power Sequencing

VCC normally connects through a high impedance (R5)

to the rectified line, with an additional path(R6) to a low

voltage, bootstrap on the winding power transformer.

VFWD normally connects to a divider (R1 and R2) from

the rectified line. For circuit activation, all of the following

considerations are required:

1.

VFWD between 1V and 4V

2.

VCC has been under 9V (to reset the shutdown

latch)

3.

VCC over 13V

from its start up value of 85

µA to its run value of 1mA.

The capacitor on SOFTST is charged with a current de-

termined by:

–

I

V

R

1

4

.

When SOFTST rises above 1V, output pulses will begin

pulses, the low voltage bootstrap winding should now

power the controller. If VCC falls below 9V, the controller

will turn off and the start sequence will reset and retry.

VCC Clamp

An internal shunt regulator clamps VCC so that it will not

exceed 15V.

Output Inhibit

During normal operation, OUT is driven high at the start

of a clock period and back low when RAMP either

crosses FEEDBK or equals 4V. If, however, any of the fol-

lowing occur, OUT is immediately driven low for the re-

mainder of the clock period:

1.

VFWD is outside the range of 1V to 4V

2.

CURLIM is greater than 0.2V

3.

FEEDBK or SOFTST is less than 1V

Normal output pulses will not resume until the beginning

of the next clock period in which none of the above con-

ditions exist.

Current Limiting

CURLIM is monitored by two internal comparators. The

current limit comparator threshold is 0.2V. If the current

limit comparator is triggered, OUT is immediately driven

low and held low for the remainder of the clock cycle,

providing pulse-by-pulse overcurrent control for exces-

charged for the remainder of the clock cycle. The charg-

ing current is

–

I

V

R

1

4

.

If repetitive cycles are terminated by the current limit

comparator causing COUNT to rise above 4V, the shut-

down latch is set. The COUNT integration delay feature

will be bypassed by the shutdown comparator which has

a 0.6V threshold. The shutdown comparator immediately

greater than

()

()

44

1

•

−

R

.

APPLICATION INFORMATION