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CY7C1475BV33-133BGC Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1475BV33-133BGC
Description  72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B
Page 11 of 32
The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.[1, 2, 3, 4, 5, 6, 7]
Truth Table
Operation
Address
Used
CE1 CE2 CE3 ZZ ADV/LD
WE
BWX
OE
CEN
CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
Read Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Dummy Read
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
Write Cycle
(Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
NOP/Write Abort
(Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Abort
(Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Ignore Clock Edge (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
-
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects
are asserted, see section Truth Table for Read/Write on page 12 for details.
2. Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 12.
3. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
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