CY7C1354DV25
CY7C1356DV25
Document #: 001-48974 Rev. *A
Page 8 of 29
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0∠A16 is loaded into
the Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25). In addition, the address for the subsequent
access (read, write, and deselect) is latched into the address
register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25) (or a subset for byte write operations, see
Write Cycle Description tables for details) inputs is latched into
the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1354DV25 and BWa,b for CY7C1356DV25)
signals. The CY7C1354DV25/CY7C1356DV25 provides Byte
Write capability that is described in the Write Cycle Description
tables. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input selectively writes to only the desired
bytes. Bytes not selected during a Byte Write operation remains
unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte Write capability is
included to greatly simplify read, modify, and write sequences,
which can be reduced to simple Byte Write operations.
Because
the
CY7C1354DV25
and
CY7C1356DV25
are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1354DV25 and DQa,b/DQPa,b for CY7C1356DV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1354DV25 and CY7C1356DV25 has an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1354DV25 and BWa,b for CY7C1356DV25) inputs must
be driven in each cycle of the burst write to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
When in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ
> V
DD − 0.2V
50
mA
tZZS
Device operation to ZZ
ZZ
> V
DD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ
< 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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