CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C
Page 6 of 30
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Input-
Synchronous
Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1392CV18 - D[7:0]
CY7C1992CV18 - D[8:0]
CY7C1393CV18 - D[17:0]
CY7C1394CV18 - D[35:0]
LD
Input-
Synchronous
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
NWS0,
NWS1
Nibble Write Select 0, 1
− Active LOW (CY7C1392CV18 Only). Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which nibble is written into the device during the
current portion of the Write operations.Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3
− Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1992CV18
− BWS
0 controls D[8:0]
CY7C1393CV18
− BWS
0 controls D[8:0], BWS1 controls D[17:9].
CY7C1394CV18
− BWS
0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (2 arrays each of 1M x 8) for CY7C1392CV18, 2M x 9 (2 arrays each of 1M x 9) for CY7C1992CV18,
1M x 18 (2 arrays each of 512K x 18) for CY7C1393CV18 and 512K x 36 (2 arrays each of 256K x 36)
for CY7C1394CV18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1392CV18 and CY7C1992CV18, 19 address inputs for CY7C1393CV18 and 18 address inputs for
CY7C1394CV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data output signals. These pins drive out the requested data during a read operation. Valid data is driven
out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock
mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1392CV18
− Q
[7:0]
CY7C1992CV18
− Q
[8:0]
CY7C1393CV18
− Q
[17:0]
CY7C1394CV18
− Q
[35:0]
R/W
Input-
Synchronous
Synchronous Read/Write input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
C
Input Clock
Positive input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See Application Example on page 9 for further details.
C
Input Clock
Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
K
Input Clock
Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
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