CY7C1354DV25
CY7C1356DV25
Document #: 001-48974 Rev. *A
Page 7 of 29
Functional Overview
The CY7C1354DV25 and CY7C1356DV25 are synchronous
pipelined Burst NoBL SRAMs designed specifically to eliminate
wait states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized
and all internal states are maintained. All synchronous opera-
tions are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.8 ns (250 MHz device).
Accesses are initiated by asserting all three Chip Enables (CE1,
CE2, CE3) active at the rising edge of the clock. If Clock Enable
(CEN) is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[d:a] can be used to conduct Byte Write opera-
tions.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW when the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core and
control logic. The control logic determines that a read access is
in progress and allows the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and onto the data bus within 2.8 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (read, write, and deselect) is initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tri-states following the next clock rise.
Burst Read Accesses
The CY7C1354DV25 and CY7C1356DV25 have an on-chip
burst counter that provides the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW to load a new address into
the SRAM, as described in the Single Read Accesses section.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst mode,
a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps
around when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enables inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
TMS
Test Mode
Select
Synchronous
Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
TCK
JTAG-Clock
Clock Input to the JTAG Circuitry.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VDDQ
I/O Power
Supply
Power Supply for the I/O Circuitry.
VSS
Ground
Ground for the Device. Should be connected to ground of the system.
NC
–
No Connects. This pin is not connected to the die.
NC (18,
36, 72,
144, 288,
576, 1G
–
These Pins are not Connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,
576M, and 1G densities.
ZZ
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Pin Definitions (continued)
Pin Name
IO
Pin Description
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