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CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Document Number: 001-12560 Rev. *E
Page 2 of 29
Logic Block Diagram (CY7C1511JV18)
Logic Block Diagram (CY7C1526JV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
21
32
8
NWS[1:0]
VREF
Write
Reg
16
A(20:0)
21
8
CQ
CQ
DOFF
Q[7:0]
8
8
8
8
Write
Reg
Write
Reg
Write
Reg
C
C
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
9
BWS[0]
VREF
Write
Reg
18
A(20:0)
21
9
CQ
CQ
DOFF
Q[8:0]
9
9
9
9
Write
Reg
Write
Reg
Write
Reg
C
C
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