2 / 30 page
CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Document Number: 001-00436 Rev. *E
Page 2 of 30
Logic Block Diagram (CY7C1510KV18)
Logic Block Diagram (CY7C1525KV18)
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
22
16
8
NWS[1:0]
VREF
Write
Reg
8
A(21:0)
22
CQ
CQ
DOFF
Q[7:0]
8
8
Write
Reg
C
C
8
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
22
18
9
BWS[0]
VREF
Write
Reg
9
A(21:0)
22
CQ
CQ
DOFF
Q[8:0]
9
9
Write
Reg
C
C
9
[+] Feedback