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ZL2105ALNFT Datasheet(PDF) 4 Page - Intersil Corporation |
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ZL2105ALNFT Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 36 page ZL2105 4 Data Sheet Revision 2/18/2009 www.intersil.com Table 3. Electrical Specifications VDDP = VDDS = 12 V, TA = -40°C to 85°C unless otherwise noted. Typical values are at TA = 25°C. Parameter Conditions Min Typ Max Unit Input and Supply Characteristics IDDS supply current fSW = 200 kHz, no load fSW = 1 MHz, no load – – 2 5 3 6 mA mA IDDL supply current fSW = 200 kHz, no load fSW = 1 MHz, no load – – 8 10 16 20 mA mA IDDS shutdown current EN = 0 V, VDDL tied to VRA, No I2C/SMBus activity – 0.7 1 mA IDDL shutdown current EN = 0 V, VDDL = 5 V, No I2C/SMBus activity – 225 500 µA VR reference output voltage VDD > 5.5 V, IVR < 5 mA 4.5 5.2 5.5 V VRA reference output voltage VDD > 5.5 V, IVRA < 35 mA 4.5 5.2 5.5 V V25 reference output voltage IV25 < 50 mA 2.25 2.5 2.75 V Output Characteristics Output Current – – 3 A Output voltage adjustment range1 VIN > VOUT 0.6 – 5.0 V Set using resistors – 10 – mV Output voltage setpoint resolution Set using I2C/SMBus – ±0.025 – % FS VSEN output voltage accuracy Includes line, load, temp -1 – 1 % VSEN input bias current VSEN = 5.5 V – 100 200 µA Set using DLY pin or resistor 7 – 200 ms Soft start delay duration range2 Set using I2C/SMBus 0.007 – 500 s Soft start delay duration accuracy – 6 – ms Set using SS pin 10 – 100 ms Soft start ramp duration range Set using resistor or via I2C 0 – 200 ms Soft start ramp duration accuracy – 100 – µs Logic Input/Output Characteristics During configuration restore -1 – 1 mA Logic input bias current (EN,PG,SCL,SDA,SALRT) Operating -10 – 10 µA MGN pin current -1 – 1 mA Logic input low, VIL – – 0.8 V Logic input OPEN (N/C) Multi-mode logic pins – 1.4 – V Logic input high, VIH 2.0 – – V Logic output low, VOL IOL ≤ 4 mA – – 0.4 V Logic output high, VOH IOH ≥ -2 mA 2.25 – – V Tracking VTRK input bias current VTRK = 5.5 V – 110 200 µA VTRK tracking accuracy 100% Tracking, VOUT - VTRK - 100 – + 100 mV Notes: 1. Does not include margin 2. The device requires approximately 6 ms following an enable signal and prior to output ramp. The minimum settable delay is 7 ms. Table 3 is continued on the following page |
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