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PRELIMINARY
CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Document Number: 001-15880 Rev. *D
Page 3 of 28
Logic Block Diagram (CY7C1568KV18)
Logic Block Diagram (CY7C1570KV18)
Write
Reg
Write
Reg
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
18
21
18
LD
Control
R/W
DOFF
18
DQ[17:0]
18
CQ
CQ
QVLD
Write
Reg
Write
Reg
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS[3:0]
VREF
36
20
36
LD
Control
R/W
DOFF
36
DQ[35:0]
36
CQ
CQ
QVLD
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