CY8C20180
Document Number: 001-17346 Rev. *F
Page 5 of 16
The CapSense Analog System
The CapSense analog system contains the capacitive sensing
hardware. which supports CapSense Successive Approximation
(CSA) algorithm. This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
Additional System Resources
System resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and power on reset (POR).
■ The I
2C slave provides 50, 100, or 400 kHz communication
over two wires.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit elimi-
nates the need for a system supervisor.
An internal 1.8V reference provides a stable internal reference
so that capacitive sensing functionality is not affected by minor
VDD changes.
I2C Interface
The two modes of operation for the I2C interface are:
■ Device register configuration and status read or write for
controller.
■ Command execution.
The I2C address is programmable during configuration. It can be
locked to prevent accidental change by setting a flag in a config-
uration register.
I2C Device Addressing
I2C device address is contained in the upper seven bits of the
first byte of a read or write transaction. The first byte of the trans-
action is used by the I2C master to address the slave. The LSB
of the byte contains the R/W bit. If this bit is 0, the master
performs write operation to the addressed slave. If this bit is 1,
the master performs read operation from the addressed slave.
The LSB(B0) is eliminated when fixing the device address. For
example, if the slave address is 02h, then the required address
is 0000010 (7 bit) excluding LSB. If write operation is performed,
the LSB is 0 and the address is 00000100(04h). If read operation
is performed, the LSB is 1 and the address is 00000101(05h).
Table 3 provides examples of I2C addressing.
CapSense Express Software Tool
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the application note “CapSense™ Express Software
Tool - AN42137” for details of the software tool.
CapSense Express Register Map
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to the CY8C201xx Register Reference Guide.
Table 3. Examples of I2C Addressing
Slave Address
Defined
B7
B6
B5
B4
B3
B2
B1
B0
Address to be
sent (in Hex) by
Master
0
000
0000
0(W)
00
0
000
0000
1(R)
01
1
000
0001
0(W)
02
1
000
0001
1(R)
03
10
000
1010
0(W)
14
10
000
1010
1(R)
15
75
100
1011
0(W)
96
75
100
1011
1(R)
97
127
111
1111
0(W)
FE
127
111
1111
1(R)
FF
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