CY8C22545 datasheet(10/27 Pages) CYPRESS

Part #	CY8C22545

Description	PSoC Programmable System-on-Chip

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 27 page

CY8C21345,

CY8C22345, CY8C22545

Document Number: 001-43084 Rev. *H

Page 10 of 27

Table 6. Register Map Bank 0 Table: User Space

PRT0DR

00

RW

40

#

ASC10CR0*

80*

RW

C0

RW

PRT0IE

01

RW

41

W

81

RW

C1

RW

PRT0GS

02

RW

42

RW

82

RW

C2

RW

PRT0DM2

03

RW

43

#

83

RW

C3

RW

PRT1DR

04

RW

44

#

ASD11CR0*

84*

RW

C4

RW

PRT1IE

05

RW

45

W

85

RW

C5

RW

PRT1GS

06

RW

46

RW

86

RW

C6

RW

PRT1DM2

07

RW

47

#

87

RW

C7

RW

PRT2DR

08

RW

48

#

88

RW

PWMVREF0

C8

#

PRT2IE

09

RW

49

W

89

RW

PWMVREF1

C9

#

PRT2GS

0A

RW

4A

RW

8A

RW

IDAC_MODE

CA

RW

PRT2DM2

0B

RW

4B

#

8B

RW

PWM_SRC

CB

#

PRT3DR

0C

RW

4C

#

8C

RW

TS_CR0

CC

RW

PRT3IE

0D

RW

4D

W

8D

RW

TS_CMPH

CD

RW

PRT3GS

0E

RW

4E

RW

8E

RW

TS_CMPL

CE

RW

PRT3DM2

0F

RW

4F

#

8F

RW

TS_CR1

CF

RW

PRT4DR

10

RW

CSD0_DR0_L

50

R

90

RW

CUR PP

D0

RW

PRT4IE

11

RW

CSD0_DR1_L

51

W

91

RW

STK_PP

D1

RW

PRT4GS

12

RW

CSD0_CNT_L

52

R

92

RW

PRV PP

D2

RW

PRT4DM2

13

RW

CSD0_CR0

53

#

93

RW

IDX_PP

D3

RW

14

RW

CSD0_DR0_H

54

R

94

RW

MVR_PP

D4

RW

15

RW

CSD0_DR1_H

55

W

95

RW

MVW_PP

D5

RW

16

RW

CSD0_CNT_H

56

R

96

RW

I2C

0_CFG

D6

RW

17

RW

CSD0_CR1

57

RW

97

RW

I2C

0_SCR

D7

#

18

RW

CSD1_DR0_L

58

R

98

RW

I2C

0_DR

D8

RW

19

RW

CSD1_DR1_L

59

W

99

RW

I2C

0_MSCR

D9

#

1A

RW

CSD1_CNT_L

5A

R

9A

RW

INT_CLR0

DA

RW

1B

RW

CSD1_CR0

5B

#

9B

RW

INT_CLR1

DB

RW

1C

RW

CSD1_DR0_H

5C

R

9C

RW

INT_CLR

2

DC

RW

1D

RW

CSD1_DR1_H

5D

W

9D

RW

INT_CLR

3

DD

RW

1E

RW

CSD1_CNT_H

5E

R

9E

RW

INT_MSK3

DE

RW

1F

RW

CSD_CR1

5F

RW

9F

RW

INT_MSK

2

DF

RW

DBC00DR0

20

#

AMX_IN

60

RW

A0

INT_MSK0

E0

RW

DBC00DR1

21

W

AMUX_CFG

61

RW

A1

INT_MSK1

E1

RW

DBC00DR2

22

RW

PWM_CR

62

RW

A2

INT_VC

E2

RC

DBC00CR0

23

#

ARF_CR

63

RW

A3

RES_WDT

E3

W

DBC01DR0

24

#

CMP_CR0

64

#

A4

DEC_DH

E4

RW

DBC01DR1

25

W

ASY_CR

65

#

A5

DEC_DL

E5

RW

DBC01DR2

26

RW

CMP_CR1

66

RW

A6

DEC _CR0*

E6

RW

DBC01CR0

27

#

67

RW

A7

DEC_CR1*

E7

RW

DCC02DR0

28

#

ADC0_CR

68

#

A8

W

MUL

0_X

E8

W

DCC02DR1

29

W

ADC1_CR

69

#

A9

W

MUL

0_Y

E9

W

DCC02DR2

2A

RW

SADC_DH

6A

RW

AA

R

MUL

0_DH

EA

R

DCC02CR0

2B

#

SADC_DL

6B

RW

AB

R

MUL

0_DL

EB

R

DCC03DR0

2C

#

TMP_DR0

6C

RW

AC

RW

ACC0_DR1

EC

RW

DCC03DR1

2D

W

TMP_DR1

6D

RW

AD

RW

ACC0_DR0

ED

RW

DCC03DR2

2E

RW

TMP_DR2

6E

RW

AE

RW

ACC0_DR3

EE

RW

DCC03CR0

2F

#

TMP_DR3

6F

RW

AF

RW

ACC0_DR2

EF

RW

DBC10DR0

30

#

70

RW

RDI0RI

B0

RW

CPU A

F0

#

DBC10DR1

31

W

71

RW

RDI0SYN

B1

RW

CPU_T1

F1

#

DBC10DR2

32

RW

ACB00CR1*

72*

RW

RDI0IS

B2

RW

CPU_T2

F2

#

DBC10CR0

33

#

ACB00CR2*

73*

RW

RDI0LT0

B3

RW

CPU_X

F3

#

DBC11DR0

34

#

74

RW

RDI0LT1

B4

RW

CPU PCL

F4

#

DBC11DR1

35

W

75

RW

RDI0RO0

B5

RW

CPU_PCH

F5

#

DBC11DR2

36

RW

ACB01CR1*

76*

RW

RDI0RO1

B6

RW

CPU_SP

F6

#

DBC11CR0

37

#

ACB01CR2*

77*

RW

RDI0DSM

B7

RW

CPU_F

F7

I

DCC12DR0

38

#

78

RW

RDI1RI

B8

RW

CPU_TST0

F8

RW

DCC12DR1

39

W

79

RW

RDI1SYN

B9

RW

CPU_TST1

F9

RW

DCC12DR2

3A

RW

7A

RW

RDI1IS

BA

RW

CPU_TST2

FA

RW

DCC12CR0

3B

#

7B

RW

RDI1LT0

BB

RW

CPU TST3

FB

#

DCC13DR0

3C

#

7C

RW

RDI1LT1

BC

RW

DAC1_D

FC

RW

Shaded fields are Reserved and must not be accessed.

# Access is bit specific. * has a different meaning.

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