CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *G
Page 11 of 52
4.11 Function Pins (FN0[0:3])
The function I/O pins are a set of dedicated control pins used to
perform system level functions with the power peripheral blocks
of the PowerPSoC. These pins are dynamically configurable,
enabling them to perform a multitude of input and output
functions. These I/Os have direct access to the input and output
of the voltage comparators, input of the hysteretic controller, and
output of the digital PWM blocks for the device. The function I/O
pins are register mapped. The microcontroller can control and
read the state of these pins and the interrupt function.
Some of the key system benefits of the function I/O are:
■ Enabling higher voltage current-sense amplifier as shown in
Figure 4-5
■ Synchronizing dimming of multiple PowerPSoC controllers as
shown in Figure 4-6
■ Programmable fail-safe monitor and dedicated shutdown of
hysteretic controller as shown in Figure 4-7
Along with the above functionality, these I/Os also provide
interrupt functionality enabling intelligent system responses to
power control lighting system status.
Figure 4-5. External CSA and FET Application
Figure 4-6. PowerPSoC in Master/Slave Configuration
Figure 4-7. Event Detection
FN0(0)
FN0(3)
FN0(2)
FN0(1)
Hysteretic Mode
Controller 0
External
Gate Drive 0
DAC0
DAC1
HVDD
GD 0
.
.
.
VLED > 32V
External CSA
Rsense
+
-
External FET
{
.
.
.
PowerPSoC
Hysteretic Mode
Controller 3
External
Gate Drive 3
DAC6
DAC7
GD 3
PowerPSoC
(Master)
FN0(0)
FN0(2)
FN0(1)
FN0(3)
FN0(x)
FN0(x)
PowerPSoC
(Slave 1)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 3)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 2)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 0)
Hysteretic
Controller
DIM
FN0(x)
FN0(x)
FN0(0)
Hysteretic Mode
Controller 0
External
Gate Drive 0
.
.
.
Event Detect
Trip
FN0(3)
Hysteretic Mode
Controller 3
Event Detect
Trip
.
.
.
External
Gate Drive 3
GD0
GD3
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