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CY8C27243-24SXIT Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY8C27243-24SXIT
Description  PSoC Programmable System-on-Chip
Download  53 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C27243-24SXIT Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Document Number: 38-12012 Rev. *M
Page 10 of 53
44-Pin Part Pinout
Table 6. Pin Definitions - 44-Pin TQFP
Pin
No.
Type
Pin Name
Description
Figure 6. CY8C27543 44-Pin PSoC Device
Digital
Analog
1
IO
P2[5]
2
IO
I
P2[3]
Direct switched capacitor block input.
3
IO
I
P2[1]
Direct switched capacitor block input.
4
IO
P4[7]
5
IO
P4[5]
6
IO
P4[3]
7
IO
P4[1]
8
Power
SMP
Switch Mode Pump (SMP) connection to external
components required.
9
IO
P3[7]
10
IO
P3[5]
11
IO
P3[3]
12
IO
P3[1]
13
IO
P1[7]
I2C Serial Clock (SCL).
14
IO
P1[5]
I2C Serial Data (SDA).
15
IO
P1[3]
16
IO
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
17
Power
Vss
Ground connection.
18
IO
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
19
IO
P1[2]
20
IO
P1[4]
Optional External Clock Input (EXTCLK).
21
IO
P1[6]
22
IO
P3[0]
23
IO
P3[2]
24
IO
P3[4]
25
IO
P3[6]
26
Input
XRES
Active high external reset with internal pull down.
27
IO
P4[0]
28
IO
P4[2]
29
IO
P4[4]
30
IO
P4[6]
31
IO
I
P2[0]
Direct switched capacitor block input.
32
IO
I
P2[2]
Direct switched capacitor block input.
33
IO
P2[4]
External Analog Ground (AGND).
34
IO
P2[6]
External Voltage Reference (VRef).
35
IO
I
P0[0]
Analog column mux input.
36
IO
IO
P0[2]
Analog column mux input and column output.
37
IO
IO
P0[4]
Analog column mux input and column output.
38
IO
I
P0[6]
Analog column mux input.
39
Power
Vdd
Supply voltage.
40
IO
I
P0[7]
Analog column mux input.
41
IO
IO
P0[5]
Analog column mux input and column output.
42
IO
IO
P0[3]
Analog column mux input and column output.
43
IO
I
P0[1]
Analog column mux input.
44
IO
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
TQFP
P2[5]
P2[4],ExternalAGND
A, I, P2[3]
P2[2], A, I
A, I, P2[1]
P2[0], A, I
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
SMP
XRES
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
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