PRELIMINARY
CY14B101KA/CY14B101MA
1 Mbit (128K x 8/64K x 16) nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-42880 Rev. *C
Revised July 09, 2009
Features
■ 1 Mbit nvSRAM
❐ 20 ns, 25 ns, and 45 ns access times
❐ Internally organized as 128K x 8 (CY14B101KA) or 64K x 16
(CY14B101MA)
❐ Hands off automatic STORE on power down with only a small
capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power down
❐ RECALL to SRAM initiated on power up or by software
■ High Reliability
❐ Infinite Read, Write, and RECALL cycles
❐ 200,000 STORE cycles to QuantumTrap
❐ 20 year data retention
■ Real Time Clock
❐ Full featured Real Time Clock
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Capacitor or battery backup for RTC
❐ Backup current of 300 nA
■ Industry Standard Configurations
❐ Single 3V +20%, –10% operation
❐ Commercial and Industrial temperatures
❐ 44-pin and 54-pin TSOP II and 48-pin SSOP packages
❐ Pb-free and RoHS compliance
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1 Mbit
nonvolatile static RAM with a full featured real time clock in a
monolithic
integrated
circuit.
The
embedded
nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
STATIC RAM
ARRAY
1024 X 1024
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
1024 X 1024
STORE
RECALL
V
CC
VCA
P
HSB
A
0 A1
A
2 A3 A4 A10 A11
SOFTWARE
DETECT
A14 -A2
OE
CE
WE
BHE
BLE
A
5
A
6
A7
A8
A9
A
12
A13
A14
A15
A16
DQ0
DQ
1
DQ2
DQ3
DQ4
DQ
5
DQ6
DQ
7
DQ8
DQ
9
DQ10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
RTC
MUX
A16-A0
Xout
Xin
INT
V
RTCbat
VRTCcap
Logic Block Diagram[1, 2, 3]
Notes
1. Address A0 - A16 for x8 configuration and Address A0 - A15 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
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