CY22801
Universal Programmable Clock Generator
(UPCG)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-15571 Rev. *B
Revised June 26, 2009
Features
■ Integrated Phase-Locked Loop (PLL)
■ Field Programmable
■ Input Frequency Range:
❐ Crystal: 8 to 30 MHz
❐ CLKIN: 1 to 133 MHz
■ LVCMOS Output Frequency:
❐ 1 to 200 MHz (Commercial Grade)
❐ 1 to 166.6 MHz (Industrial Grade)
■ Low Jitter, High Accuracy Outputs
■ 3.3V Operation
■ Commercial and Industrial Temperature Ranges
■ 8-Pin SOIC Package
Benefits
■ Inventory of only one device, CY22801, used in various
applications
■ In-house programming of sample and prototype quantities is
made available using the CY36800 InstaClock kit
■ Input and output frequencies are customized to suit your needs
■ High-performance PLL is tailored for multiple applications
■ Critical timing requirements met in complex system designs
■ Application compatibility enabled
Pin Configuration
Figure 1. CY22801 8-Pin SOIC
OUTPUT
DIVIDERS
XTAL
OSC
XOUT
PLL
XIN/CLKIN
CLKA
CLKB
CLKC
Logic Block Diagram
1
2
3
4
XOUT
CLKB
VSS
CLKC
CLKA
5
6
7
8
VDD
XIN/CLKIN
NC
Table 1. Pin Definition
Name
Pin Number
Description
XIN
1
Reference Input: Crystal or External Clock
VDD
2
3.3V Voltage Supply
NC
3
No Connect; leave this pin floating
VSS
4
Ground
CLKB
5
Clock Output B
CLKA
6
Clock Output A
CLKC
7
Clock Output C
XOUT
8
Reference Output: Connect to external crystal. When the reference is an external clock signal
(applied to pin 1), this pin is not used and must be left floating.
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