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Spread Aware™, Ten/Eleven Output Zero Delay Buffer
CY2509/10
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07230 Rev. *C
Revised July 01, 2005
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Well suited to both 100- and 133-MHz designs
• Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL
outputs
• 50 ps typical peak cycle-to-cycle jitter
• Single output enable pin for CY2510 version, dual pins
on CY2509 devices allow shutting down a portion of the
outputs
• 3.3V power supply
• On board 25
Ω damping resistors
• Available in 24-pin TSSOP package
• Improved tracking skew, but narrower frequency
support limit when compared to W132-09B/10B
Key Specifications
Operating Voltage: ................................................3.3V±10%
Operating Range: ....................... 40 MHz < fOUT < 140 MHz
Cycle-to-Cycle Jitter: ................................................ <100 ps
Output to Output Skew: ........................................... <100 ps
Phase Error Jitter:..................................................... <100 ps
Block Diagram
Pin Configurations
Q0
PLL
Q1
Q2
Q3
Q5
Q6
OE0:4
Q7
Q8
FBOUT
Q4
Q9
OE
OE5:8
Configuration of these blocks dependent upon specific option being used
FBIN
CLK
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
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