2

UCC1858

UCC2858

UCC3858

ABSOLUTE MAXIMUM RATINGS

Gate Drive Current

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2A

Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

Input Current IAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature . . . . . . . . . . . . . . . . . . .

−65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . .

−55°C to +150°C

Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C

Analog Inputs

Maximum Forced Voltage . . . . . . . . . . . . . . . . –0.3V to 11V

Unless otherwise indicated, voltages are reference to ground and cur-

rents are positive into, negative out of the specified terminal. Pulsed is

defined as a less than 10% duty cycle with a maximum duration of

500ns. Consult Packaging Section of Databook for thermal limitations

and considerations of packages.

Controller improvements include an onboard peak detec-

tor for the input line RMS voltage, an integrated

overcurrent shutdown, overvoltage shutdown and signifi-

cantly lower quiescent operating current. The peak de-

tector eliminates an external 2-pole low pass filter for

RMS detection. This simplifies the converter design as

well as providing an approximate 6X improvement in in-

put line transient response. The current signal is ex-

tracted from the current error amplifier input to provide a

cycle-by-cycle peak current limit. Low startup and oper-

ating currents which are achieved through the use of

Unitrode’s BCDMOS process simplify the bootstrap

supply design as well as minimize losses in the control

circuit. A transconductance voltage error amplifier allows

output voltage sensing for internal overvoltage protection.

Additional features include: undervoltage lockout for reli-

able off-line startup, a precision 7.5V reference, and a

precision RMS detection and signal conditioning circuit.

Chip shutdown can be attained by bringing the FBL pin

below 0.5V.

DESCRIPTION (cont.)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Overall

Supply Current, Off

100

250

µA

Supply Current, On

FBL = 0V

2

3.5

5

mA

VDD Turn-On Threshold

12

13.5

15.5

V

VDD Turn-Off Threshold

10

V

UVLO Hysteresis

3.2

3.5

3.8

V

Voltage Amplifier

Input Voltage

2.95

3

3.05

V

Over Voltage Protection

Volts Above VA– Input Voltage

0.12

0.14

0.16

V

VA– Bias Current

–0.5

–1

µA

Open Loop Gain

45

50

dB

VAO High

Load = –25

µA

5.7

6

6.3

V

VAO Low

Load = 25

µA

0.3

0.5

V

Output Source Current

–50

µA

Output Sink Current

50

µA

Transconductance

400

600

1000

µS

VDD

OUT

GND

RT

CT

SYNC

FBM

FBL

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CRMS

IAC

VAO

CAO

VA–

MOUT

VREF

CA–

CONNECTION DIAGRAM

DIP-16, SOIC-16 (TOP VIEW)

J, N, DW Packages