CY25200
Document #: 38-07633 Rev. *E
Page 8 of 11
Absolute Maximum Rating
Supply Voltage (VDD)....................................... –0.5 to +7.0V
DC Input Voltage ......................................–0.5V to VDD + 0.5
Storage Temperature (non-condensing) ..... –55
°C to +125°C
Junction Temperature ................................ –40
°C to +125°C
Data Retention at Tj = 125
°C ................................> 10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
Description
Comments
Min
Typ.
Max
Unit
FNOM
Nominal Crystal Frequency
Parallel resonance, fundamental mode,
AT cut
830
MHz
CLNOM
Nominal Load Capacitance
Internal load caps
6
30
pF
R1
Equivalent Series Resistance (ESR) Fundamental mode
25
Ω
R3/R1
Ratio of Third Overtone Mode ESR
to Fundamental Mode ESR
Ratio used because typical R1 values are
much less than the maximum specification
3
DL
Crystal Drive Level
No external series resistor assumed
0.5
2
mW
Recommended Operating Conditions
Parameter
Description
Min
Typ.
Max
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
VDDLHI
Operating Voltage
3.135
3.3
3.465
V
VDDLLO
Operating Voltage
2.375
2.5
2.625
V
TAC
Ambient Commercial Temp
0
–
70
°C
CLOAD
Maximum Load Capacitance VDD/VDDL = 3.3V
–
–
15
pF
CLOAD
Maximum Load Capacitance VDDL = 2.5V
–
–
15
pF
FSSCLK-HighVoltage SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL = 3.3 V
3
–
200
MHz
FSSCLK-LowVoltage SSCLK1/2/3/4 when VDD = AVDD = 3.3.V and VDDL = 2.5V
3
–
166
MHz
REFOUT
REFOUT when VDD = AVDD = 3.3.V and VDDL = 3.3V or 2.5V
8
–
166
MHz
fREF1
Clock Input
8
–
166
MHz
fREF2
Crystal Input
8
–
30
MHz
tPU
Power up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
DC Electrical Specifications
Parameter[2]
Name
Description
Min
Typ.
Max
Unit
IOH3.3
Output High Current
VOH = VDD – 0.5V, VDD/VDDL = 3.3V
10
12
–
mA
IOL3.3
Output Low Current
VOL = 0.5V, VDD/VDDL = 3.3V
10
12
–
mA
IOH2.5
Output High Current
VOH = VDDL – 0.5V, VDDL = 2.5V
8
16
–
mA
IOL2.5
Output Low Current
VOL = 0.5V, VDDL = 2.5V
8
16
–
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
–
1.0
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0–
0.3
VDD
IVDD
[3]
Supply Current
AVDD/VDD Current
–
–
33
mA
IVDDL2.5
[3]
Supply Current
VDDL Current (VDDL = 2.625V)
–
–
20
mA
IVDDL3.3
[3]
Supply Current
VDDL Current (VDDL = 3.465V)
–
–
26
mA
IDDS
Power Down Current
VDD = VDDL = AVDD = 3.465V
–
–
50
uA
IOHZ
IOLZ
Output Leakage
VDD = VDDL = AVDD = 3.465V
–
–
10
uA
Notes
2. Not 100% tested, guaranteed by design.
3. IVDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks.
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