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CY22150
Document #: 38-07104 Rev. *I
Page 2 of 16
Pin Configuration
Figure 1. 16-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
SCLK
LCLK1
XIN
XOUT
VDD
SDAT
AVSS
LCLK3
LCLK2
CLK6
CLK5
AVDD
VDDL
LCLK4
Table 1. Pin Definitions
Name
Number
Description
XIN
1
Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal,
regardless of manufacturer, process, performance, or quality
VDD
2
3.3V Voltage Supply
AVDD
3
3.3V Analog Voltage Supply
SDAT
4
Serial Data Input
AVSS
5
Analog Ground
VSSL
6
LCLK Ground
LCLK1
7
Configurable Clock Output 1 at VDDL level (3.3V or 2.5V)
LCLK2
8
Configurable Clock Output 2 at VDDL level (3.3V or 2.5V)
LCLK3
9
Configurable Clock Output 3 at VDDL level (3.3V or 2.5V)
SCLK
10
Serial Clock Output
VDDL
11
LCLK Voltage Supply (2.5V or 3.3V)
LCLK4
12
Configurable Clock Output 4 at VDDL level (3.3V or 2.5V)
VSS
13
Ground
CLK5
14
Configurable Clock Output 5 (3.3V)
CLK6
15
Configurable Clock Output 6 (3.3V)
XOUT[1]
16
Reference Output
Note
1. Float XOUT if XIN is driven by an external clock source.
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