CY22150
Document #: 38-07104 Rev. *I
Page 3 of 16
Frequency Calculation and Register Definitions
The CY22150 is an extremely flexible clock generator with four
basic variables that are used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider, which
can be a fixed or calculated value. There are three formulas to
determine the final output frequency of a CY22150 based
design:
■ CLK = ((REF * P)/Q)/Post Divider
■ CLK = REF/Post Divider
■ CLK = REF.
The basic PLL block diagram is shown in Figure 2. Each of the
six clock outputs on the CY22150 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be applied
to the calculated VCO frequency ((REF*P)/Q) or to the REF
directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Figure 2. Basic Block Diagram of CY22150 PLL
(Q+2)
VCO
(2(PB+4)+PO)
/2
/3
/2
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[45H,46H]
REF
PFD
Divider Bank 1
[45H]
DIV1SRC [OCH]
/4
DIV2SRC [47H]
Divider Bank 2
DIV1N [OCH]
DIV2N [47H]
/DIV1N
1
0
1
0
[42H]
[40H], [41H], [42H]
/DIV2N
Qtotal
Ptotal
CLKOE [09H]
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