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CY14B104LA, CY14B104NA
Document #: 001-49918 Rev. *B
Page 11 of 23
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 12, 16]
Figure 8. SRAM Write Cycle #1: WE Controlled[3, 15, 16, 17]
Address Valid
Address
Data Output
Output Data Valid
Standby
Active
High Impedance
CE
OE
BHE, BLE
ICC
t
HZCE
t
RC
t
ACE
t
AA
t
LZCE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
PU
t
PD
t
HZBE
t
HZOE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
Previous Data
t
WC
t
SCE
t
HA
t
BW
t
AW
t
PWE
t
SA
t
SD
t
HD
t
HZWE
t
LZWE
WE
BHE, BLE
CE
Note
17. CE or WE must be >VIH during address transitions.
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