CY62177DV30
MoBL®
Document #: 38-05633 Rev. *C
Page 5 of 11
Data Retention Waveform[10, 11]
VCC, min.
VCC, min.
tCDR
VDR > 1.5V
tR
CE
or
VCC
BHE
.BLE
DATA RETENTION MODE
Switching Characteristics Over the Operating Range[11, 12]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
10
10
ns
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to LOW Z[13]
5
5
ns
tHZOE
OE HIGH to High Z[13, 14]
20
25
ns
tLZCE
CE LOW to Low Z[13]
10
10
ns
tHZCE
CE HIGH to High Z[13, 14]
20
25
ns
tPU
CE LOW HIGH to Power-Up
0
0
ns
tPD
CE HIGH to Power-Down
55
70
ns
tDBE
BLE/BHE LOW to Data Valid
55
70
ns
tLZBE
BLE/BHE LOW to Low Z[13]
10
5
ns
tHZBE
BLE/BHE HIGH to HIGH Z[13, 14]
20
25
ns
WRITE CYCLE[15]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
40
60
ns
tAW
Address Set-Up to Write End
40
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tBW
BLE/BHE LOW to Write End
40
60
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High-Z[13, 14]
20
25
ns
tLZWE
WE HIGH to Low-Z[13]
10
10
ns
Notes:
10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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