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UCC2913 Datasheet(PDF) 3 Page - Texas Instruments |
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UCC2913 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 9 page 3 UCC1913 UCC2913 UCC3913 ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = –55°C to +125°C for UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; IVDD = 2mA, CT = 4.7pF, TA = TJ PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Power Limiting Section VSENSE Regulator Voltage IPL = 64 A 4.35 4.85 5.35 V Duty Cycle Control IPL = 64µA 0.6 1.2 1.7 % IPL = 1mA 0.045 0.1 0.17 % Overload Section Delay to Output (Note 1) 300 500 ns Output Sink Current VSENSE = VIMAX = 300mV 40 100 mA Threshold Relative to IMAX 140 200 260 mV Note 1: Guaranteed by design. Not 100% tested in production. CT: A capacitor is connected to this pin in order to set the maximum fault time. The maximum fault time must be more than the time to charge external load capacitance. The maximum fault time is defined as: () T CT I FAULT CH = • 2 where IA I CH PL =+ 36 µ , and IPL is the current into the power limit pin. Once the fault time is reached the output will shutdown for a time given by: TCT SD =• • 2 106 IMAX: This pin programs the maximum allowable sour- cing current. Since VDD is a regulated voltage, a voltage divider can be derived from VDD to generate the pro- gram level for the IMAX pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin over the current sense resistor. If desired, a controlled current startup can be pro- grammed with a capacitor on the imax pin, and a pro- grammed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. OUT: Output drive to the MOSFET pass element. PL: This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this pin to the drain of the NMOS pass element. When the voltage across the NMOS exceeds 5V, current will flow into the PL pin which adds to the fault timer charge current, reducing the duty cycle from the 3% level. When IPL>>36µA then the average MOSFET power dissipation is given by: PIMAX R FET avg PL () =• • • − 110 6 SENSE: Input voltage from the current sense resistor. When there is greater than 50mV across this pin with re- spect to VSS, then a fault is sensed, and CT starts to charge. SD/FLT: This pin provides fault output indication and shutdown control. Interface into and out of this pin is usu- ally performed through level shift transistors. When 20 µA is sourced into this pin, shutdown drives high causing the output to disable the NMOS pass device. When opened, and under a non-fault condition, the SD/FLT pin will pull to a low state. When a fault is detected by the fault timer, or undervoltage lockout, this pin will drive to a high state, indicating the output FET is off. VDD: Current driven with a resistor to a voltage at least 10V more positive than VSS. Typically a resistor is con- nected to ground. The 10V shunt regulator clamps VDD at 10V above the VSS pin, and is also used as an output reference to program the maximum allowable sourcing current. VSS: Ground reference for the IC and the most negative voltage available. PIN DESCRIPTIONS |
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