4

UCC18500/1/2/3

UCC28500/1/2/3

330pF.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Peak Current Limit Section

PKLMT Reference Voltage

–15

0

15

mV

PKLMT Propogation Delay

300

ns

Multiplier Section

High Line, Low Power

–6

A

High Line, High Power

–90

A

Low Line, Low Power

–19

A

Low Line, High Power

–300

A

IAC Limited

–300

A

Gain Constant (K)

1

1/V

Zero Current

0

–2

A

0

–2

A

–3

µA

Power Limit

–420

W

Zero Power Section

Zero Power Comparator Threshold

Measured on VAOUT

0.10

0.25

0.40

V

PFC Gate Driver Section

GT1 Pull Up Resistance

7

GT1 Pull Down Resistance

3

GT1 Output Rise Time

25

ns

GT1 Output Fall Time

10

ns

Maximum Duty Cycle

94

%

Second Stage UVLO (UVLO2)

PWM Turn-on Reference (UCCX8500/501)

6.30

6.75

7.30

V

Hysteresis (UCCX8500/501)

1.2

V

PWM Turn-on Reference (UCCX8502/503)

6.30

6.75

7.30

V

Hysteresis (UCCX8502/503)

3V

Second Stage Soft Start Section

SS2 Charge Current

–7.5

–10

–12.5

µA

VERR

300

mV

SS2 Discharge Current

ENA = High, UVLO = Low, SS2 = 2.5V

3

10

mA

Second Stage Duty Cycle Clamp Section

Maximum Duty Cycle

44

50

%

Second Stage Pulse by Pulse Current Sense Section

Current Sense Comparator Threshold

VERR = 2.5V, Measured on ISENSE2

.95

1.05

1.15

V

Second Stage Over Current Limit Section

Peak Current Comparator Threshold

1.15

1.30

1.45

V

Input Bias Current

50

nA

Second Stage Gate Driver Section

GT2 Pull Up Resistance

7

GT2 Pull Down Resistance

3

GT2 Output Rise Time

25

ns

GT2 Output Fall Time

25

ns

Note 1: Guaranteed by design, not 100% tested in production.