5

UCC1946

UCC2946

UCC3946

Figure 5. Reset circuit timings.

t4: Voltage glitch occurs, but is filtered at the RTH pin,

RES remains high.

t5: Voltage glitch occurs whose magnitude and duration

returned and RES is pulled high.

is asserted.

UDG-97067

Connecting WDO to RES

In order to provide design flexibility, the reset and watch-

dog circuits in the UCC3946 have separate outputs. Each

output will independently drive high or low, depending on

circuit conditions explained previously.

In some applications, it may be desirable for either the

RES or WDO to reset the microprocessor. This can be

done by connecting WDO to RES. If the pins try to drive

to different output levels, the low output level will domi-

nate. Additional current will flow from VDD to GND during

these states. If the application cannot support additional

current (during fault conditions), RES and WDO can be

connected to the inputs of an OR gate whose output is

connected to the microprocessor’s reset pin.

Layout Considerations

A 0.1

mended to decouple the UCC3946 from switching tran-

Since RP and WP are precision current sources, capaci-

with minimal trace length to reduce board capacitance.

Care should be taken to route any traces with high volt-

age potential or high speed digital signals away from

these capacitors.

Resistors R1 and R2 generally have a high ohmic value,

traces associated with these parts should be kept short

in order to prevent any transient producing signals from

coupling into the high impedance RTH pin.

APPLICATION INFORMATION (cont.)