3

UCC1807-1/-2/-3

UCC2807-1/-2/-3

UCC3807-1/-2/-3

COMP: COMP is the output of the error amplifier and the

input of the PWM comparator. The error amplifier in the

UCC3807 is a low output impedance, 2MHz operational

amplifier. COMP can both source and sink current. The

error amplifier is internally current limited, which allows

zero duty cycle by externally forcing COMP to GND.

The UCC3807 family features built-in full cycle soft start.

Soft start is implemented as a clamp on the maximum

COMP voltage.

CS: Current sense input. There are two current sense

comparators on the chip, the PWM comparator and an

overcurrent comparator.

The UCC3807 also contains a leading edge blanking cir-

cuit, which disconnects the external CS signal from the

current sense comparator during the 100ns interval im-

mediately following the rising edge of the signal at the

OUT pin. In most applications, no analog filtering is re-

quired on CS. Compared to an external RC filtering tech-

nique, leading edge blanking provides a smaller effective

CS to OUT propagation delay. Note, however, that the

minimum non-zero on-time of the OUT signal is directly

affected by the leading edge blanking and the CS to

OUT propagation delay.

The overcurrent comparator is only intended for fault

sensing. Exceeding the overcurrent threshold causes a

soft start cycle.

FB: The inverting input to the error amplifier. For best

stability, keep connections to FB as short as possible and

stray capacitance as small as possible.

GND: Reference ground and power ground for all func-

tions of the part.

OUT: The output of a high current power driver capable

of driving the gate of a power MOSFET with peak cur-

rents exceeding 1A. OUT is actively held low when VDD

is below the UVLO threshold.

The high current power driver consists of MOSFET out-

put devices in a totem pole configuration. This allows the

output to switch from VDD to GND. The output stage

also provides a very low impedance which minimizes

overshoot and undershoot. In most cases, external

Schottky clamp diodes are not required.

PIN DESCRIPTIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Start Threshold

UCCx807-1 (Note 4)

6.6

7.2

7.8

V

UCCx807-2

11.5

12.5

13.5

V

UCCx807-3

4.1

4.3

4.5

V

Minimum Operating Voltage After Start

UCCx807-1 (Note 4)

6.3

6.9

7.5

V

UCCx807-2

7.6

8.3

9.0

V

UCCx807-3

3.9

4.1

4.3

V

Hysteresis

UCCx807-1

0.1

0.3

0.5

V

UCCx807-2

3.5

4.2

5.1

V

UCCx807-3

0.1

0.2

0.3

V

Soft Start Section

COMP Rise Time

FB = 1.8V, From 0.5V to 4.0V

4

ms

Overall Section

Startup Current

VDD < Start Threshold (UCCx807-1,-3)

0.1

0.2

mA

VDD < Start Threshold (UCCx807-2)

0.15

0.25

mA

Operating Supply Current

FB = 0V, CS = 0V, No Load (Note 7)

1.3

2.1

mA

VDD Zener Shunt Voltage

12.0

13.5

15.0

V

Shunt to Start Difference

0.5

1.0

V

Note 1: Measured at TRIG; signal minimum = 1/3 VDD, maximum = 2/3 VDD.

Note 2: Gain is defined by: A

V

V

COMP

CS

,0

0.8V

Note 3: Parameter measured at trip point of latch with FB at 0V.

Note 4: Start Threshold and Zener Shunt thresholds track one another.

Note 5: Ensured by design. Not 100% tested in production.

Note 6: Adjust VDD above the start threshold before setting at 10V for UCC3807-2.

Note 7: Does not include current in external timing RC network.