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UCC3580DTR-2G4 Datasheet(PDF) 6 Page - Texas Instruments |
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UCC3580DTR-2G4 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 16 page  6 UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 The soft start pin provides an effective means to start the IC in a controlled manner. An internal current of 20 A begins charging a capacitor connected to SS once the startup conditions listed above have been met. The voltage on SS effectively controls maximum duty cycle on OUT1 during the charging period. OUT2 is also con- trolled during this period (see Figure 1). Negation of any of the startup conditions causes SS to be immediately discharged. Internal circuitry ensures full discharge of SS (to 0.3V) before allowing charging to begin again, provided all the startup conditions are again met. Oscillator Simplified oscillator block diagram and waveforms are shown in Figure 3. OSC1 and OSC2 pins are used to program the frequency and maximum duty cycle. Capac- itor CT is alternately charged through R1 and discharged through R2 between levels of 1.67 V and 3.3 V. The charging and discharging equations for CT are given by VC(cha rge ) = • 1 • e - t 1 VREF - æ è ç ö ø ÷ 2 3 t VC(dis cha rge ) = V e REF - t 2 2 3 ·· t where t1 =R1•CT and t2 = R2 • CT. The charge time and discharge time are given by tCH = 0.69 • R1 • CT and tDIS =0.69•R2•CT The CLK output is high during the discharge period. It blanks the output to limit the maximum duty cycle of OUT1. The frequency and maximum duty cycle are given by () Fre que ncy = 1.44 (R1+ R2) • CT + 27 pF Ma ximum Duty Cycle = R1 R1+ R2 Maximum Duty Cycle for OUT1 will be slightly less due to Delay1 which is programmed by R3. Voltage Feedforward and Volt-Second Clamp UCC3580 has a provision for input voltage feedforward. As shown in Figure 3, the ramp slope is made propor- tional to input line voltage by converting it into a charging current for CR. This provides a first order cancellation of the effects of line voltage changes on converter perfor- mance. The maximum volt-second clamp is provided to protect against transient saturation of the transformer core. It terminates the OUT1 pulse when the RAMP volt- age exceeds 3.3V. If the feedforward feature is not used, the ramp can be generated by tying R4 to REF. How- ever, the linearity of ramp suffers and in this case the maximum volt-second clamp is no longer available. Figure 3. Oscillator and ramp circuits. UDG-96016-1 Delay Times 0 200 400 600 800 1000 1200 1400 0 100 200 300 400 500 600 700 800 900 1000 R3 ProgrammingResistor k W 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 Delay Ratio Delay1 Delay2 Figure 2. Delay times. APPLICATION INFORMATION (cont.) |
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