TE

CH

tm

Preliminary T35L3232B

Taiwan Memory Technology, Inc. reserves the right

P. 15

Publication Date: FEB. 2000

to change products or specifications without notice.

Revision:0.A

PIPELINE READ/WRITE TIMING

A4

High-Z

BURST READ

C LK

ADS C

AD S P

A D D RE S S

B W E

B W 1 - B W 4

t KC

t KH t KL

t ADSS t ADSH

DO N' T CARE

UNDEFINED

t AS t AH

t WS t WH

t CES t CEH

t DH

t KQ

tOELZ

tOEHZ

t DS

t KQ

t KQLZ

Single WRITE

Q(A1)

Q(A2)

Q(A3)

Q(A4)

Q(A4+1)

Q(A4+3)

Q(A4+2)

A5

A3

A1

(NOTE1)

CE

( N O T E 2 )

ADV

O E

D

A2

A6

Q

High-Z

D(A3)

D(A5)

D(A6)

Back-to-Back READs

Pass-through

READ

Back-to-Back

WRITEs

Note: 1. Q(A4) refers to output from address A4.

Q (A4 + 1) refers to output from the next internal burst

address following A4.

2. CE2 and CE2 have timing identical to CE .

On this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH.

When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an

ADSP , ADSC or ADV

cycle is performed.

4. GW is HIGH.

5. Back-to-back READs may be controlled by either ADSP or ADSC.