TE

CH

tm

T35L6432B

Taiwan Memory Technology, Inc. reserves the right

P.7

Publication Date: JUL. 2002

to change products or specifications without notice.

Revision: A

TRUTH TABLE

OPERATION

ADDRESS

USED

CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power Down

None

H

X

X

L

X

L

X

X

X

L-H

High-Z

Deselected Cycle, Power Down

None

L

X

L

L

L

X

X

X

X

L-H

High-Z

Deselected Cycle, Power Down

None

L

H

X

L

L

X

X

X

X

L-H

High-Z

Deselected Cycle, Power Down

None

L

X

L

L

H

L

X

X

X

L-H

High-Z

Deselected Cycle, Power Down

None

L

H

X

L

H

L

X

X

X

L-H

High-Z

Snooze Cycle, Power Down

None

X

X

X

H

X

X

X

X

X

X

High-Z

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

H

L-H

High-Z

WRITE Cycle, Begin Burst

External

L

L

H

L

H

L

X

L

X

L-H

D

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

H

L-H

High-Z

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

High-Z

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

High-Z

WRITE Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

WRITE Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H

High-Z

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H

High-Z

WRITE Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

WRITE Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one

or more byte write enable signals

2.

write to DQ17-DQ24.

3. All inputs except

must meet setup and hold times around the rising edge ( LOW

to HIGH) of CLK.

4. Suspending burst generates wait cycle.

5. For a write operation following a read operation.

OE

must be HIGH before the input data

required setup time plus High-Z time for

OE

and staying HIGH throughout the input data

hold time.

6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.

edge of

CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H

edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.