Electronic Components Datasheet Search |
|
SPT5420SIM Datasheet(PDF) 4 Page - Cadeka Microcircuits LLC. |
|
SPT5420SIM Datasheet(HTML) 4 Page - Cadeka Microcircuits LLC. |
4 / 8 page 4 6/26/01 SPT5420 PARAMETER SYMBOL MIN TYP MAX UNIT Address Valid to WR Setup t1 20 ns Address Valid to WR Hold t2 0ns CS Pulse Width Low t3 50 ns WR Pulse Width Low t4 50 ns CS to WR Setup t5 0ns WR to CS Hold t6 0ns Data Setup t7 25 ns Data Hold t8 0ns Settling Time1 t9 15 us LDAC Pulse Width Low t10 50 ns CLR Pulse Activation t11 300 ns NOTES: All digital input rise and fall times are measured from 10% to 90% of +5 V. tr = tf = 5 ns. 1. RL = 10 kΩ CL ≤ 220 pF TIMING CHARACTERISTICS t5 t3 t6 t4 t1 t2 t7 t8 t10 CS WR A0A2 D0D12 LDAC t9 VOUT t5 t3 t6 t4 t1 t2 t7 t8 CS WR A0A2 D0D12 t9 VOUT t11 t9 CLR VOUT Figure 1a – Timing Diagram: Latched Mode (LDAC Strobed) Figure 1b – Timing Diagram: Transparent Mode (LDAC Held Low) |
Similar Part No. - SPT5420SIM |
|
Similar Description - SPT5420SIM |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |