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SPT7730SCS Datasheet(PDF) 5 Page - Cadeka Microcircuits LLC. |
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SPT7730SCS Datasheet(HTML) 5 Page - Cadeka Microcircuits LLC. |
5 / 8 page 5 12/19/97 SPT7730 Figure 1 - Analog Input Full-Scale Range VREF+ 6% of [(VREF+) - (VREF-)] VREF- +FS -FS 4% of [(VREF+) - (VREF-)] The drive requirements for the analog input are minimal when compared to most other converters due to the SPT7730’s extremely low input capacitance of only 5 pF and very high input resistance of greater than 5 M Ω. If the input buffer amplifier supply voltages are greater than VDD + 0.7 V or less than Ground - 0.7 V, the analog input should be protected through a series resistor and a diode clamping circuit as shown in figure 2. Figure 2 - Recommended Input Protection Circuit 47 Ω D1 D2 ADC Buffer AVDD +V -V D1 = D2 = Hewlett Packard HP5712 or equivalent INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 3. This circuit provides ESD robustness to >3.0 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. Figure 3 - On-Chip Protection Circuit VDD Analog Pad 120 Ω 120 Ω MODES OF OPERATION The SPT7730 has three modes of operation.The mode of operation is based strictly on how the SC is used. SINGLE SHOT MODE When SC goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). The MSB of data is valid 8 ns after the falling edge of the fourth conversion clock. (See figure 8.) The conversion is complete after 12 clock cycles. At the falling edge of the twelfth clock cycle, if SC is high (not selected), the data output goes to a high impedance state, and no more conversions will take place until the next SC low event. (See the single shot mode timing diagram in figure 4.) SYNCHRONIZED MODE When SC goes low, conversion will start on the next rising edge of the clock (defined as the first conversion clock). The MSB is valid 8 ns after the falling edge of the fourth conver- sion clock. The first conversion is complete after 12 clock cycles. At any time after the falling edge of the twelfth clock cycle, SC may go low again to initiate the next conversion. When the SC goes low, the conversion starts on the rising edge of the next clock. (See the synchronized mode timing diagram in figure 5.) The data output will go to a high impedance state until the next conversion is initiated. FREE RUN MODE When SC goes low, conversion starts on the next rising edge of the clock (defined as the first conversion clock). The MSB data is valid 8 ns after the falling edge of the fourth conver- sion clock. As long as SC is held low, the device operates in the free run mode. New conversions start after every twelfth cycle with valid data available 8 ns after the falling edge of the fourth clock within each new conversion cycle. The data output remains low between conversion cycles. (See the free run mode timing diagram in figure 6.) |
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