5

October 2002

SPT7755

TYPICAL INTERFACE CIRCUIT

The circuit in figure 1 is intended to show the most elabo-

rate method of achieving the least error by correcting for

integral linearity, input induced distortion, and power sup-

ply/ground noise. This is achieved by the use of external

reference ladder tap connections, input buffer, and supply

decoupling. Please contact the factory for the SPT7755

evaluation board application note that contains more

details on interfacing the SPT7755. The function of each

pin and external connections to other components is as

follows:

The power supply pins should be bypassed as close to the

device as possible with at least a .01 µF ceramic capaci-

tor. A 10 µF tantalum can also be used for low frequency

suppression. DGND is the ground for the ECL outputs and

is to be referenced to the output pulldown voltage and ap-

propriately bypassed as shown in figure 1.

There are two analog input pins that are tied to the same

point internally. Either one may be used as an analog input

sense and the other for input force. This is convenient for

testing the source signal to see if there is sufficient drive

capability. The pins can also be tied together and driven by

the same source. The SPT7755 is superior to similar de-

vices due to a preamplifier stage before the comparators.

This makes the device easier to drive because it has con-

stant capacitance and induces less slew rate distortion.

The clock inputs are designed to be driven differentially

with ECL levels. The duty cycle of the clock should be kept

at 50% to avoid causing larger second harmonics. If this is

not important to the intended application, then duty cycles

other than 50% may be used.

The digital outputs can drive 50 Ω to ECL levels when

pulled down to –2 V. When pulled down to –5.2 V, the out-

puts can drive 130 Ω to 1 kΩ loads. All digital outputs are

ommends using differential receivers on the outputs of the

data ready lines to ensure the proper output rise and fall

times.

There are two reference inputs and one external reference

ence pins and tap can be driven by op amps as shown in

operation. These voltage inputs can be bypassed to

AGND for further noise suppression if so desired.

Table I – Output Coding

D8

D7 . . . D8

>–0.5 LSB

1

1 0 0 0 0 0 0 0

–0.5 LSB

1

1 0 0 0 0 0 0 0

01 0 0 0 0 0 0 0

–1.5 LSB

0

1 0 0 0 0 0 0 0

01 0 0 0 0 0 0 1

••

•

••

•

••

•

–1.0 V

0

1 1 0 0 0 0 0 0

00 1 0 0 0 0 0 0

••

•

••

•

••

•

–2.0 V +0.5 LSB

0

0 0 0 0 0 0 0 1

00 0 0 0 0 0 0 0

<(–2.0 V +0.5 LSB)

0

0 0 0 0 0 0 0 0

Indicates the transition between the two codes

THERMAL MANAGEMENT

The typical thermal impedance is as follows:

ΘCA = +17 °C/W in still air with no heat sink

We highly recommend that a heat sink be used for this

device with adequate air flow to ensure rated performance

of the device. We have found that a Thermalloy 17846

heat sink with a minimum air flow of 1 meter/second (200

linear feet per minute) provides adequate thermal perfor-

mance under laboratory tests. Application specific condi-

tions should be taken into account to ensure that the

device is properly heat sinked.

grey code with the coding as shown in table I. CADEKA rec-