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TMC2192 Datasheet(PDF) 10 Page - Cadeka Microcircuits LLC. |
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TMC2192 Datasheet(HTML) 10 Page - Cadeka Microcircuits LLC. |
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10 / 69 page  TMC2192 PRODUCT SPECIFICATION 10 REV. 1.0.0 8/13/03 Synchronization Modes Control Registers for this section The TMC2192 offers a variety of synchronization modes; these are master, slave, genlock, 656 mode, and DRS-Lock. In master mode, the TMC2192 generates its own timing and the synchronization is supplied externally by HSOUT and VSOUT signals. In slave and genlock modes the TMC2192 derives its timing from the input pins HSIN, VSIN. In 656 mode the timing is driven by the synchronization codes embedded into the data stream. Master The TMC2192 drives the output pins HSOUT and VSOUT to synchronize the incoming video. A new color frame starts at the rising edge of RESET. The encoder always starts at the 1st vertical serration in field 8 and will freerun the field and line sequence. The control register bit SRESET can be used to synchronize the start of the field and line sequence in mas- ter mode by resetting the FVHGEN state machine. Output synchronization signal VSOUT can operate in a traditional sync mode or in a MPEG style field toggle mode. Slave The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. CCIR656 The TMC2192 derives all synchronization from the embed- ded TRS (timing reference signals) information. Blanking of selected lines is determined by the v bit of the TRS. However the control registers VBIENx can override and blank the active video portion of VBI lines regardless of the state of the v-bit. Genlock The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. The TMC2192 collects GRS data and resets its subcarrier phase and frequency to the data embed- ded in the GRS stream. The GRS detection occurs only on the CBVS port. DRS The TMC2192 is driven by the input synchronization pins HSIN and VSIN. When the falling edge of HSIN and VSIN occurs at the same rising edge of PXCK the TMC2192 will start a new field.VSIN can be either a traditional pulse or the MPEG style field toggle. In both cases the TMC2192 will flywheel through fields 2, 4, 6, and 8 synchronizing only to fields 1, 3, 5, and 7. Subcarrier phase adjustment is deter- mined by the DRS data. The DRS detection can occur on either the CBVS port or the pixel data port. Propagation Delay The propagation delay from the pixel data (PD) input to the D/A output is 64 PXCK’s. Figure 8 shows the propagation delay for both master and slave synchronization modes. For CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the midpoint of sync and is 32 PXCK’s (24 PXCK’s in PAL) after the EAV TRS. Figure 7. Propagation Delay through the Encoder Address Bit(s) Name 0x06 5-3 MODE 0x06 1 TOUT 0x06 0 TSOUT PD[23:14] PXCK DACx (ANALOG) DCVBS (D[7:0],FLD[2:1]) 65-6294-09 CB0 CBn Y0 COMP0 COMP1 Yn CRn Yn+1 tDO tDO 0 63 65 128 n = (SY+BR+BU+CBP+AV)*2 Midpoint of the Falling Edge of Sync HSOUT HSIN (TSOUT = 1) |
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Similar Description - TMC2192 |
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