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TMC22071AR1C Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC.

Part # TMC22071AR1C
Description  Genlocking Video Digitizer
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Manufacturer  CADEKA [Cadeka Microcircuits LLC.]
Direct Link  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

TMC22071AR1C Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC.

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TMC22071A
PRODUCT SPECIFICATION
8
Figure 4. Control Register Map
Control Register Bit Functions
Bit
Name
Function
0
SRESET
Software reset. When LOW, resets and holds internal state machines, resets Control
Register with previously written values, and disables output drivers. When HIGH,
SRESET starts and runs state machines, PXCK, and enables outputs.
1-3
FORMAT
Input signal format select.
Bit 3 is the MSB.
000 NTSC at 12.27 Mpps.
001 NTSC at 13.5 Mpps.
010 Reserved.
011 Reserved.
100 PAL at 13.5 Mpps.
101 Reserved.
11x Reserved.
4-6
TEST
Factory test control bits. These should be set LOW.
7,8
SOURCE
Video source select. Bit 8 is the MSB.
00 VIN1
01 VIN2
1x VIN3
9
VGAIN
Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X.
10-11
TEST
Factory test control bits. These should be set LOW.
12-16
SUBPIX
These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by
-16/32 to +15/32 pixels. Bit 16 is the two’s complement MSB. When SUBPIX is 00h,
HSYNC and incoming video are subject to LEADLAG. A value of 18h delays HSYNC
1/4 pixel. A value of 08h advances HSYNC 1/4 pixel.
17-24
LEADLAG
This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV
cycles. When LEADLAG is 7Bh, HSYNC and incoming video are in alignment. A value of
83h delays HSYNC eight LDV cycles. A value of 73h advances HSYNC eight LDV
cycles. Bit 24 is the MSB.
0
00
0 0 0
000 00
00
1
00 0
7
8
15 16
23
24
31 32
39 40
46
47
54
STATUS REGISTER
65-22071-06
55
58


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