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TMC3033KRC50 Datasheet(PDF) 9 Page - Cadeka Microcircuits LLC. |
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TMC3033KRC50 Datasheet(HTML) 9 Page - Cadeka Microcircuits LLC. |
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9 / 12 page  PRODUCT SPECIFICATION TMC3033 9 Applications Discussion Figure 4 illustrates a typical TMC3033 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal volt- age reference source. Grounding It is important that the TMC3033 power supply is well- regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video sig- nals at the output of the circuit. The TMC3033 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individu- ally decoupled at the pin. Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board lay- out. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOR, IOG, IOB) as short as possible and as far as possi- ble from all digital signals. The TMC3033 should be located near the board edge, close to the analog output connectors. 2. The power plane for the TMC3033 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC3033 is the same as that of the system's digital circuitry, power to the TMC3033 should be decoupled with 0.1 µF and 0.01µF capacitors and isolated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC3033, the voltage reference, or the analog outputs. Capacitive cou- pling of digital power supply noise from this layer to the TMC3033 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Related Products • TMC3503 Triple 8-bit 80 Msps D/A Converters • TMC1175A 40 Msps CMOS 8-bit A/D Converter • TMC1275 40 Msps CMOS 8-bit A/D Converter • TMC22091, TMC22191 Digital Video Encoders • TMC2242C/TMC2243/TMC2246A Video Filters • TMC2249A Digital Mixer • TMC2250A Matrix Multiplier • TMC2272A Colorspace Converter • TMC2302 Image Manipulation Sequencer • TMC2340A Digital Synthesizer • TMC2081 Digital Video Mixer Figure 4. Typical Interface Circuit 65-3033-04 R9-0 G9-0 B9-0 +3.3V 0.1 µF 10 µF VDD GND TMC3033 Triple 10-bit D/A Converter CLK SYNC BLANK RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK COMP VREF RREF +3.3V 0.1 µF 0.1 µF 572 Ω 3.3k Ω LM185-1.2 (Optional) IOR IOG IOB 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω ZO=75Ω ZO=75Ω ZO=75Ω Red Green Blue |
Similar Part No. - TMC3033KRC50 |
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