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ADC180 Datasheet(PDF) 3 Page - RHOPOINT COMPONENTS |
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ADC180 Datasheet(HTML) 3 Page - RHOPOINT COMPONENTS |
3 / 7 page THEORY OF OPERATION The ADC180 uses a differential input to improve accuracy. To measure single source voltages, V low should be connected to the ground point of the source voltage to be measured. In figure 1, the switch is shown in the normal operating mode connecting V hi and Vlow to the differential input of the transadmittance amplifier. For an autozero cycle, V hi is disconnected and the input to the amplifier is shorted. The charge balance modulator (figure 2) uses a proprietary patented architecture to achieve the high accuracy of the ADC180 without any error correction method other than autozero. This enables the converter to sample the output of the transadmittance amplifier continuously at a sampling rate of 20 MHz. This is important for applications like inertial guidance systems where Auto Zero Switch Charge Balance Modulator Microprocessor Output Buffer Crystal Clock Transadmittance Amplifier V hi V low Auto Zero Data Request Status Lines Output Enable Data Output 13 . . . 20 21 29 22 23 24 34 35 39 40 FIGURE 1. BLOCK DIAGRAM Bidirectional Curent Source ∫ Direction Switch Bilevel Comparator Figure 2. Patented Charge Balance Modulator The conversion result between two consecutive data request inputs at times t 1 and t 2 is mathematically represented by the equation Data Output I IN ADC180DS REV I FEB 05 Duty Cycle Test Point 3 20MHz clock output 26 The converter provides two 32 bit data words with the first word containing t 2-t1 and the second word containing ∫ ⋅ − = 2 1 1 2 1 t t inp iav dt V t t V dt V t t inp ⋅ ∫ 2 1 dt V t t inp ⋅ ∫ 2 1 must be measured without any loss of time increments. The output of the charge balance modulator is in the form of a pulse width modulation signal. The internal microprocessor provides all control functions and digital signal processing. The converter also has an internal crystal clock to avoid phase jitter errors and a tristate output buffer for easy interface with bus based systems. For the data output timing see figures 5 and 6. |
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