CONNECTING THE ADC180

DUTY CYCLE OUTPUT (pin 3)

This logic level output allows monitoring of the

integration cycle and is usually used for timing

purposes.

POWER SUPPLIES (pins 4-7)

The ADC180 has internal 0.1µF decoupling

capacitors for all power supply inputs.

This is

sufficient for applications with relatively short power

supply leads (approx. 5") or if additional capacitors

are located on the circuit board. External capacitors

of 10 µF on the ±15V inputs and 33 µF on the +5V

input is recommended for applications with longer

power supply leads.

GROUND (pin7)

Since ground noise can result in a loss of accuracy,

the ground connection should be made as solid as

possible. Use of a ground plane is a good approach

to maintain the full accuracy of the ADC180.

OUTPUT DATA LINES (pins 13-20)

The parallel output data is available on pins 13-20.

Pin 20 is the Most Significant Bit and pin 13 the

Least Significant Bit. The data lines go to a high

impedance state when the Output Enable line is at a

logic 1 level.

ANALOG INPUTS (pins 39,40)

The differential analog inputs are buffered by

op amps and have a common mode rejection of

approximately 80dB minimum. To maintain the full

accuracy of the ADC180 it is recommended to

maintain the input to analog low to less than

0.1VDC. To avoid differential noise pickup, parallel

adjacent lines should be used for the analog inputs

on PC boards and shielded lines outside of the PC

connections.

CAPACITOR (pin 34, 35)

The only external component required to operate

the ADC180 is a capacitor which sets the

integration time. A 0.082µF capacitor results in an

integration time of approximately 250 µs.

For

2,000µs a 0.68µF capacitor is required.

The

relationship is linear for intermediate capacitor

values.

The main parameter affected by shorter conversion

times

is

bias

stability

over

temperature.

Polystyrene, mylar, or polycarbonate capacitors are

recommended.

AUTO ZERO / RESET (pin 29)

A logic 0 on this input will autozero the ADC180 by

internally connecting the analog high to analog low.

Since the internal microprocessor is reset, the

ADC180 is not functional during this time

(approximately 1s). S

that no data is available.

After completing the

autozero function, S

ADC will begin collecting data.

STATUS LINES (pins 23, 24)

These lines indicate the present state of the ADC.

After a data request has been received and the

current integration cycle is complete, the ADC will

output the data collected subsequent to the

previous data request.

S

acknowledge the data request. The 8 bytes of data

will be placed on the data bus sequentially. A logic

1 on S

the data has been transmitted, S

logic 0.

DATA REQUEST (pin 22)

A logic 0 on this line initiates a data transfer

sequence.

OUTPUT ENABLE (pin 21)

A logic 0 on this line enables outputs D0 - D7.

NC= Factory test points, do not connect to these pins.

Vee (-15V)

Vcc (+15V)

Vdd (+5V)

(TOP VIEW)

ADC180

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

N.C.

Duty Cycle Output

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

D0

D1

D2

D5

D4

D3

D6

D7

GND

ANALOG LOW

ANALOG HIGH

/AUTO ZERO / RESET

S1

S0

/DATA REQUEST

/OUTPUT ENABLE

CAPACITOR

FIGURE 3. EXTERNAL CONNECTIONS

ADC180DS REV I FEB 05

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.