Serial Data Timing Diagram

30073303

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is

sent from the shift registers to an actual counter. A slew rate of at least 30 V/

μs is recommended for these signals. After the

programming is complete, the CLK, DATA, and LE signals should be returned to a low state. If the CLK and DATA lines are toggled

while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be

degraded during the time of this programming.

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