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DS34T102 Datasheet(PDF) 1 Page - Maxim Integrated Products |
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DS34T102 Datasheet(HTML) 1 Page - Maxim Integrated Products |
1 / 16 page ABRIDGED DATA SHEET ________________________________________________________ Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standards- based TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. With built-in full- featured E1/T1 framers and LIUs. These ICs encapsulate the TDM-over-packet solution from analog E1/T1 signal to Ethernet MII while preserving options to make use of TDM streams at key intermediate points. The high level of integration available with the DS34T10x devices minimizes cost, board space, and time to market. Applications TDM Circuit Extension Over PSN o Leased-Line Services Over PSN o TDM Over GPON/EPON o TDM Over Cable o TDM Over Wireless Cellular Backhaul Over PSN Multiservice Over Unified PSN HDLC-Based Traffic Transport Over PSN Functional Diagram Features Full-Featured IC Includes E1/T1 LIUs and Framers, TDMoP Engine, and 10/100 MAC Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments 64 Independent Bundles/Connections Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet VLAN Support According to 802.1p and 802.1Q 10/100 Ethernet MAC Supports MII/RMII/SSMII Selectable 32-Bit, 16-Bit or SPI Processor Bus Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing Glueless SDRAM Buffer Management Low-Power 1.8V Core, 3.3V I/O See detailed feature list in Section 5. Ordering Information PART PORTS TEMP RANGE PIN-PACKAGE DS34T101GN 1 -40 C to +85C 484 TEBGA DS34T101GN+ 1 -40 C to +85C 484 TEBGA DS34T102GN 2 -40 C to +85C 484 TEBGA DS34T102GN+ 2 -40 C to +85C 484 TEBGA DS34T104GN 4 -40 C to +85C 484 TEBGA DS34T104GN+ 4 -40 C to +85C 484 TEBGA DS34T108GN 8 -40 C to +85C 484 HSBGA DS34T108GN+ 8 -40 C to +85C 484 HSBGA +Denotes a lead(Pb)-free/RoHS-compliant package (explanation). CPU Bus Octal E1/T1/J1 Transceiver LIUs Framers Clock Inputs TDM Access BERT & CAS xMII Buffer Manager Circuit Emulation Engine Clock Adapters 10/100 Ethernet MAC E1/T1 Interfaces SDRAM Interface DS34T108 19-4835; Rev 6; 8/09 |
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